The invention relates to semiconductor fabrication. More specifically, the invention relates to the fabrication of retrograde well structures in CMOS devices.
Complementary Metal Oxide Semiconductor (CMOS) technology involves the pairing of complementary n-channel and p-channel MOS transistors to form low power integrated circuits. Each pair of complementary transistors is formed in close proximity on a substrate, with the p-channel transistor being formed in a heavily n-doped region of the substrate, and the n-channel transistor being formed in a heavily p-doped region. Low power consumption has made CMOS the technology of choice for very large scale integrated circuits, such as microprocessors, dynamic random access memories (DRAMS) and erasable programmable read only memories (EPROMS).
A major problem with CMOS devices is known as "latch-up." With the p-channel and n-channel transistors being in close proximity, conditions can arise that allow large currents to flow between the drain of one transistor and the source of the complementary transistor. The large currents, in turn, cause high power dissipation, which can stop the CMOS device from functioning or even destroy the CMOS device.
Latch-up can arise from voltage overshoot or undershoot at the terminals of the CMOS device, avalanche breakdown at the well-substrate junction, or device degradation that causes current to be shunted through the device. Avalanche breakdown can result from high voltages at the terminals, ionizing radiation, external voltage transients, or large charge buildups at the substrate-well interface. Device degradation could be caused by punch-through between the substrate region and the source/drain region of the device in the well, or avalanche ionization near the drain due to hot-electron effects.
Latch-up in a CMOS device can be prevented by the use of a retrograde well structure. Unlike a conventional well, which is formed by implanting and diffusing a dopant to a desired depth, a retrograde well structure is formed by performing deep implants to place the dopant at its desired depths without further diffusion. Resulting is a deep peak concentration below the surface and a negative slope approaching the surface (that is, a decreasing concentration towards the surface). The high concentration of dopants implanted near the well bottom shunts the carriers and prevents latch-up from occurring.
The deep implants for the n-wells are made by high energy implanters. U.S. Pat. No. 5,404,042 suggests an implant energy of 1.5 MeV for the deep implants. Although less energy can be used, the implanter still must be capable of performing implants at energies between 300 keV and 700 keV. Such implanters are commercially available, but they are very expensive.
Low energy implanters, which perform implants at energies of 220 keV and less, are also commercially available. They are also far less expensive than high energy implanters. If they could perform the deep implants, their usage would lower the cost of fabricating CMOS devices having retrograde well structures. However, using known techniques, the low energy implanters do not have sufficient energy to implant the dopants at the required depths in the substrate. Consequently, only high energy implanters are used at the present time for forming the retrograde well structures.
It is an objective of the invention to form retrograde well structures using low energy implanters.